This present invention relates generally to a semiconductor integrated circuit (SIC) formed of a plurality of chips of different types.
The level of SIC integration, especially the level of DRAM integration, has been increased rapidly in recent years, in other words the number of devices per chip has been quadruplicated every three years. System on silicon, which is a structure capable of mounting one system on one chip, is no longer an impracticable idea.
Meanwhile, recent improvements in packaging technology expedites an approach of forming one system with a plurality of chips. NIKKEI MICRODEVICES (pp. 90-91, published February 1994 shows a multi-chip module (MCM) that is implemented by mounting chips with their surfaces facing each other by means of a face-to-face packaging technique.
Conventional packaging techniques, however, have some drawbacks. There are constraints on the type of terminal and on the placement/location of terminals and, conventionally, only specific chips are allowed to be mounted onto a single chip.
FIG. 14 is a conceptual diagram useful in understanding prior art packaging technique problems. A mother chip X, in combination with a subsidiary chip x, is mounted, and a mother chip Y, in combination with a subsidiary chip y, is mounted, and a mother chip Z, in combination with a subsidiary chip z, is mounted. An interface section 91 of the mother chip X corresponds to only the subsidiary chip x and an interface section 94 of the subsidiary chip x corresponds to only the mother chip X. An interface section 92 of the mother chip Y corresponds to only the subsidiary chip y and an interface section 95 of the subsidiary chip y corresponds to only the mother chip Y. An interface section 93 of the mother chip Z corresponds to only the subsidiary chip z and an interface section 96 of the subsidiary chip z corresponds to only the mother chip Z.
Accordingly, when trying to mount the mother chip X in combination with the subsidiary chip y, the interface section 91 of the mother chip X must be re-designed for correspondence with the subsidiary chip y and, additionally, the interface section 95 of the subsidiary chip y must be re-designed for correspondence with the mother chip X. For example, when mounting the subsidiary chip x onto each of the mother chips X, Y, Z, three different subsidiary chips which have the same function as the subsidiary chip x and which are designed in such a way as to correspond to the mother chips X, Y, Z respectively must be prepared. As the number of combinations of subsidiary chips and mother chips increases, much more time is required for the design of chips and the cost of manufacturing chips increases.